The present invention relates to integrated circuit devices and related fabrication methods and, more particularly, to integrated circuit capacitors and methods of fabricating integrated circuit capacitors.
Generally, it is useful to form three-dimensional capacitors having a cylindrical shape in order to improve capacitance. However, as the design rule of integrated circuit devices decreases to 0.2 xcexcm or less, the use of cylindrical capacitors may present some problems.
Now referring to FIGS. 1 through 4, cross-sectional views of intermediate structures that illustrate a conventional method of fabricating integrated circuit capacitors will be described. As illustrated in FIG. 1, an insulating layer 13 is formed on an integrated circuit substrate 11, for example, a silicon substrate. The insulating layer 13 may include a silicon oxide layer. A titanium nitride (TiN) plug 15 is formed in the insulating layer 13. A lower mold layer 17 may be formed on the insulating layer 13 and the TiN plug 15. The lower mold layer 17 may be formed of silicon oxide. An etch stop layer 19 may be formed on the lower mold layer 17 and may be formed of silicon nitride. An upper mold layer 21 may be formed on the etch stop layer 19 and may be formed of silicon oxide.
Now referring to FIG. 2, a contact hole 22 may be formed by patterning the upper mold layer 21, the etch stop layer 19, and the lower mold layer 17 that exposes the TiN plug 15. A conductive layer 23 for a U-shaped lower electrode may be formed over the surface of the existing integrated circuit. The conductive layer 23 for the U-shaped lower electrode may be formed of, for example, metals of a platinum group, such as platinum (Pt), ruthenium (Ru), and iridium (Ir). A sacrificial layer 25 may be formed on the conductive layer 23 and may fill the contact hole 22. The sacrificial layer 25 may include, for example, a photoresist layer or a silicon oxide layer.
Now referring to FIG. 3, the sacrificial layer 25 and the U-shaped lower electrode 23 are etched using the surface of the upper mold layer 21 as an etch stop point. As illustrated in FIG. 4, a U-shaped lower electrode 23 of a capacitor is formed by removing the sacrificial layer 25 and the upper mold layer 21 using a wet etching method. A dielectric layer (not shown) and an upper electrode (not shown) may be formed over the entire surface of the integrated circuit device to complete the conventional integrated circuit capacitor. Conventional capacitors typically have poor adhesion between the lower electrode 23 and the etch stop layer pattern 19 when the upper mold layer 21 is removed. Consequently, an oxide etchant used to remove the upper mold layer 21 may penetrate into the lower mold layer 17 as illustrated by the arrows in FIG. 4. This penetration may cause the lower mold layer 17 and the insulating layer 13 to be damaged. The possible damage to the lower mold pattern 17 is illustrated by reference numeral 27 in FIG. 4.
Integrated circuits, according to embodiments of the present invention, Provide an electrically insulating electrode support layer having an opening therein, on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
In further embodiments of the present invention the second capacitor dielectric layer does not extend on the inner surface of the U-shaped lower electrode. The electrically insulating electrode support layer may include a mold layer on the integrated circuit substrate and an etch stop layer on the mold layer. The mold layer may include silicon oxide and the etch stop layer may include at least one of silicon nitride and/or tantalum oxide.
In some embodiments of the present invention, the first capacitor dielectric layer may further extend onto the support layer. The first capacitor dielectric layer may include a tantalum oxide, aluminum oxide (Al2O3), and/or Hafnium Oxide (HfO2). The second capacitor dielectric layer may include a dielectric material that is not etched by and oxide etchant.
Still further embodiments of the present invention provide methods of fabricating integrated circuit capacitors that include the steps of forming an electrically insulating electrode support layer having an opening therein, on an integrated circuit substrate. The method further includes forming a U-shaped lower electrode in the opening and forming a first capacitor dielectric layer extending on an inner surface and outer portion of the U-shaped lower electrode. A second capacitor dielectric layer is formed extending between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extending between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode is formed on the first capacitor dielectric layer.
In some embodiments of the present invention, forming the electrically insulating electrode support layer may include forming a mold layer on the integrated circuit substrate and forming an etch stop layer on the mold layer. The lower mold layer may have a thickness of from about 5 to about 20 percent of the thicknesses of the lower mold layer, the etch stop layer and an upper mold layer combined.
In further embodiments of the present invention the first capacitor dielectric layer may have a thickness of from about 100 xc3x85 to about 200 xc3x85 and the second capacitor dielectric layer may have a thickness of about 10 xc3x85 to about 40 xc3x85. The U-shaped lower electrode may have a thickness of from about 200 to about 500 xc3x85.